1. Field of the Invention
The present invention relates to a method of accurately forming a desired pattern on a major surface of a semiconductor substrate which has been warped because of a brazing on a metal plate or the like, and also relates to a method of manufacturing a semiconductor device through the patterning procedure.
2. Description of Background Art
As well known in the art, a high-power semiconductor device often has a semiconductor substrate fixed on a metal plate. FIG. 8 is a schematic sectional view showing a semiconductor substrate 51 employed in a gate turn-off thyristor (GTO), where a bottom major surface of the semiconductor substrate 51 is brazed to a molybdenum plate 53 through an anode electrode 52 serving as a brazing material layer. The molybdenum plate 53 functions as a supporting plate or a reinforcing plate for the semiconductor substrate 51. On a top major surface of the semiconductor substrate 51, a plurality of emitter regions 54 are disposed. The emitter regions 54 are concentrically arranged around the center C of the semiconductor substrate 51, and cathode electrodes 55 are formed on them. For the convenience of explanation, a layer structure of active regions in the semiconductor substrate 51 and an arrangement of gate electrodes on the top major surface are omitted in FIG. 8. On the other hand, a mask 56 used in patterning the emitter regions 54 and a mask 57 used in patterning the cathode electrodes 55 are shown in FIG. 8.
In a process of brazing the semiconductor substrate 51 to the molybdenum plate 53, both of them are high in temperature. When aluminum is used as brazing material, the semiconductor substrate 51 and the molybdenum plate 53 are heated to a temperature equal to or higher than 660.degree. C., which is a fusing point of aluminum. Then, an assembly 58 consisting of the semiconductor substrate 51 and the molybdenum plate 53 is cooled to around the room temperature after the process of brazing, and correspondingly, the assembly 58 is warped in accordance with a difference between their respective thermal expansion coefficients.
When the semiconductor substrate 51 is made of silicon, its thermal expansion coefficient is 4.15.times.10.sup.-6 /K, while the thermal expansion coefficient of the molybdenum plate 53 is 5.1.times.10.sup.-6 /K, which is larger than the former. This causes the assembly 58 to be warped with the semiconductor substrate 51 curved in a convex shape after the cooling down. In FIG. 8, a part of an assembly 59 which is identical with the assembly 58 after warped is shown by a broken line. For convenience, however, the warping is exaggerated in FIG. 8.
On the other hand, with regard to the emitter regions 54 and cathode electrodes 55 on the top major surface of the semiconductor substrate 51, the formers are formed before the above-mentioned brazing process, while the latters are formed after the brazing process. Thus, even if a registration within the patterns of the masks 56 and 57 is perfect, the cathode electrodes 55 are not accurately superimposed on the emitter regions 54 because of the warping of the semiconductor substrate 51, so that misregistration is caused therebetween.
When the misregistration is relatively small, there arises not much of a problem, but when it is large, a part of the cathode electrode 55 is formed out the emitter regions 54, as shown in an enlarged plan view of FIG. 9(a) and an enlarged sectional view of FIG. 9(b). As a result, the emitter regions 54 and other active regions (not shown) around the same are short circuited, and consequently the GTO does not work well.
The important thing is that the degree of the misregistration depends upon various factors and does not keep constant. More particularly, the misregistration of the emitter regions 54 and the cathode electrodes 55 depends upon the distances between the emitter regions 54 and the center C in FIG. 8. This is because the curvature of the assembly 59 is relatively small around the center of the substrate 51 while the curvature is relatively large at regions near to the circumferential edge of the substrate 51, as understood in FIG. 8. The warping of the assembly 59 also varies depending upon the thickness of the molybdenum plate 53 and the thickness of the semiconductor substrate 51.
For example, when the semiconductor substrate 51 is 0.6 mm in thickness and the molybdenum plate 53 is 66 mm in diameter, the warping of the semiconductor substrate 51 varies in accordance with the thickness of the molybdenum plate 53 as shown in FIG. 10, where the "degree of warping" in FIG. 10 means a transformation amount of the semiconductor substrate 51 at its edges. Accordingly, the degree of the misregistration of the emitter regions 54 and the cathode electrodes 55 also depends upon the thickness of the molybdenum plate 53 and the semiconductor substrate 51.
Even in the same conditions, many semiconductor substrates have a statistical dispersion in warping degree when they are brazed, but do not have an identical value. Thus, the degrees of the disagreement in positions of the cathode electrodes 55 are not the same, and therefore, the misregistration cannot be prevented by uniformly changing the positions where the cathode electrodes 55 are formed.
Such a problem becomes serious when the patterns on the semiconductor substrate 51 are made fine to enhance the integration in the device structure. In the GTO, the fine patterns are necessary to enhance a turn-off capability, but it causes the cathode electrodes 55 to be formed out the emitter regions 54 even when misregistration therebetween is very little. With semiconductor devices other than the GTO, it is also necessary to prevent patterns from being in misregistration because of warping of a semiconductor substrate when the patterns are made fine.